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low phase noise, fast settling pll frequency synthesizer adf4193 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features new, fast settling, fractional-n pll architecture single pll replaces ping-pong synthesizers frequency hop across gsm band in 5 s with phase settled by 20 s 0.5 rms phase error at 2 ghz rf output digitally programmable output phase rf input range up to 3.5 ghz 3-wire serial interface on-chip, low noise differential amplifier phase noise figure of merit: ?216 dbc/hz loop filter design possible using adi simpll applications gsm/edge base stations phs base stations instrumentation and test equipment general description the adf4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. its architecture is specifically designed to meet the gsm/edge lock time requirements for base stations. it consists of a low noise, digital phase frequency detector (pfd), and a precision differential charge pump. there is also a differential amplifier to convert the differential charge pump output to a single-ended voltage for the external voltage-controlled oscillator (vco). the - based fractional interpolator, working with the n divider, allows programmable modulus fractional-n division. additionally, the 4-bit reference (r) counter and on-chip frequency doubler allow selectable reference signal (refin) frequencies at the pfd input. a complete phase-locked loop (pll) can be implemented if the synthesizer is used with an external loop filter and a vco. the switching architecture ensures that the pll settles inside the gsm time slot guard period, removing the need for a second pll and associated isolation switches. this decreases cost, complexity, pcb area, shielding, and characterization on previous ping-pong gsm pll architectures. functional block diagram 05328-001 n counter sw1 cp out+ cp out? sw2 reference data le 24-bit data register clk ref in a gnd 1 a gnd 2 d gnd 1 d gnd 2 d gnd 3 sd gnd sw gnd v dd dgnd lock detect r div n div sdv dd dv dd 1 dv dd 2 dv dd 3 a v dd 1 v p 1 v p 2 v p 3r set output mux mux out ? + high z phase frequency detector adf4193 fractional interpolator modulus reg fraction reg integer reg rf in+ rf in? 2 doubler 4-bit r counter /2 divider charge pump ? + + ? differential amplifier cmr ain? ain+ a out sw3 figure 1.
adf4193 rev. b | page 2 of 28 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 11 reference input section............................................................. 11 rf input stage............................................................................. 11 register map.................................................................................... 14 frac/int register (r0)........................................................... 15 mod/r register (r1) ................................................................ 16 phase register (r2) .................................................................... 17 function register (r3) .............................................................. 18 charge pump register (r4) ...................................................... 19 power-down register (r5) ....................................................... 20 mux register (r6) ...................................................................... 21 programming .................................................................................. 22 worked example ........................................................................ 22 spur mechanisms ....................................................................... 22 power-up initialization ............................................................. 23 changing the frequency of the pll and the phase look-up table ............................................................................................. 23 applications..................................................................................... 25 local oscillator for a gsm base station ................................ 25 interfacing ................................................................................... 27 pcb design guidelines for chip scale package .................... 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 6/06rev a. to rev. b changes to table 1............................................................................ 3 changes to figure 32...................................................................... 18 changes to power-up initialization section............................... 23 changes to timer values for tx section and timer values for rx section ........................................................................................ 25 11/05rev 0. to rev. a updated format..................................................................universal changes to features section............................................................ 1 changes to table 1............................................................................ 3 changes to reference input section ............................................ 11 changes to rf n divider section ................................................ 11 changes to the lock detect section ............................................ 13 changes to figure 29...................................................................... 15 changes to the 8-bit int value section ..................................... 15 changes to figure 33...................................................................... 19 replaced figure 35 ......................................................................... 21 changes to the - and lock detect modes section................ 21 changes to the power-up initialization section ........................ 23 changes to table 8.......................................................................... 23 changes to the local oscillator for a gsm base station section ....................................................................... 25 changes to the timer values for rx section .............................. 25 changes to figure 36...................................................................... 26 updates to the outline dimensions ............................................ 28 changes to the ordering guide ................................................... 28 4/05revision 0: initial version
adf4193 rev. b | page 3 of 28 specifications av dd = dv dd = sdv dd = 3 v 10%, v p 1, v p 2 = 5 v 10%, v p 3 = 5.35 v 5%, agnd = dgnd = gnd = 0 v, r set = 2.4 k, dbm referred to 50 , t a = t min to t max , unless otherwise noted. table 1. parameter b version 1 unit test conditions/comments rf characteristics rf input frequency (rf in ) 0.4/3.5 ghz min/max see figure 21 for input circuit rf input sensitivity C10/0 dbm min/max maximum allowable prescaler output frequency 2 470 mhz max ref in characteristics ref in input frequency 300 mhz max for f > 120 mhz, set ref/2 bit = 1 ref in edge slew rate 300 v/s min ref in input sensitivity 0.7/v dd v p-p min/max ac-coupled 0 to v dd v max cmos-compatible ref in input capacitance 10 pf max ref in input current 100 a max phase detector phase detector frequency 26 mhz max charge pump i cp up/down high value 6.6 ma typ with r set = 2.4 k low value 104 a typ with r set = 2.4 k absolute accuracy 5 % typ r set range 1/4 k min/max nominally r set = 2.4 k i cp three-state leakage 1 na typ i cp up vs. down matching 0.1 % typ 0.75 v v cp v p C 1.5 v i cp vs. v cp 1 % typ 0.75 v v cp v p C 1.5 v i cp vs. temperature 1 % typ 0.75 v v cp v p C 1.5 v differential amplifier input current 1 na typ output voltage range 1.4/(v p 3 ? 0.3) v min/max vco tuning range 1.8/(v p 3 ? 0.8) v min/max output noise 7 nv/hz typ @ 20 khz offset logic inputs v ih , input high voltage 1.4 v min v il , input low voltage 0.7 v max i inh , i inl , input current 1 a max c in , input capacitance 10 pf max logic outputs v oh , output high voltage v dd C 0.4 v min i oh = 500 a v ol , output low voltage 0.4 v max i ol = 500 a power supplies av dd 2.7/3.3 v min/v max dv dd av dd v p 1, v p 2 4.5/5.5 v min/v max av dd v p 1, v p 2 5.5 v v p 3 5.0/5.65 v min/v max v p 1, v p 2 v p 3 5.65 v i dd (av dd + dv dd + sdv dd ) 27 ma max 22 ma typ i dd (v p 1 + v p 2) 27 ma max 22 ma typ i dd (v p 3) 30 ma max 24 ma typ i dd power-down 10 a typ
adf4193 rev. b | page 4 of 28 parameter b version 1 unit test conditions/comments sw1, sw2, and sw3 r on (sw1 and sw2) 65 typ r on sw3 75 typ noise characteristics 900 mhz output 3 C108 dbc/hz typ @ 5 khz offset and 26 mhz pfd frequency 1800 mhz output 4 C102 dbc/hz typ @ 5 khz offset and 13 mhz pfd frequency phase noise figure of merit 5 C216 dbc/hz typ @ vco output with dither off 1 operating temperature range is from C40c to +85c. 2 the prescaler value is chosen to ensure that the rf input is divided down to a frequency that is less than this value. 3 f refin = 26 mhz; f step = 200 khz; f rf = 900 mhz; loop bw = 40 khz. 4 f refin = 13 mhz; f step = 200 khz; f rf = 1850 mhz; loop bw = 60 khz. 5 calculated from the phase noise measured at 5 khz with a 60 khz loop bw. increased noise contribution from the differential am plifier if the loop bw is reduced. timing characteristics av dd = dv dd = 3 v 10%, v p 1, v p 2 = 5 v 10%, v p 3 = 5.35 v 5%, agnd = dgnd = gnd = 0 v, r set = 2.4 k, dbm referred to 50 , t a = t min to t max , unless otherwise noted. table 2. parameter limit (b version) 1 unit test conditions/comments t 1 10 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 15 ns min clock high duration t 5 15 ns min clock low duration t 6 10 ns min clock to le setup time t 7 15 ns min le pulse width 1 operating temperature is from ?40c to +85c. 05238-002 clk data db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) le le t 2 t 4 t 5 t 3 t 7 t 6 t 1 figure 2. timing diagram
adf4193 rev. b | page 5 of 28 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd C0.3 v to +3.6 v av dd to dv dd , sdv dd C0.3 v to +0.3 v v p to gnd C0.3 v to +5.8 v v p to av dd C0.3 v to +5.8 v digital i/o voltage to gnd C0.3 v to v dd + 0.3 v analog i/o voltage to gnd C0.3 v to v p + 0.3 v ref in , rf in+ , rf in? to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial (b version) C40c to +85c storage temperature range C65c to +125c maximum junction temperature 150c lfcsp ja thermal impedance (paddle soldered) 27.3c/w reflow soldering peak temperature 260c time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv, and it is esd sensitive. proper precautions need to be taken for handling and assembly. transistor count 75,800 (mos), 545 (bjt) esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adf4193 rev. b | page 6 of 28 pin configuration and fu nction descriptions 05328-003 1 cmr 2 a out 3 sw3 4 a gnd 1 5 rf in? 6 rf in+ 7 av dd 1 24 v p 2 23 r set 22 a gnd 2 21 d gnd 3 20 v p 1 19 le 18 data 17 clk 8 d v dd 1 adf4193 top view 9 d gnd 1 10 dv dd 2 11 ref in 12 d gnd 2 13 dv dd 3 14 sd gnd 15 sdv dd 16 mux out 32 v p 3 31 ain+ 30 cp out+ 29 sw1 28 sw gnd 27 sw2 26 cp out? 25 ain? pin 1 indicator figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 cmr common-mode reference voltage for the differential amplifiers output voltage swing. internally biased to three-fifths of v p 3. requires a 0.1 f capacitor to ground. 2 a out differential amplifier output to tune the external vco. 3 sw3 fast-lock switch 3. closed wh ile sw3 timeout counter is active. 4 a gnd 1 analog ground. this is the ground return pin fo r the differential amplifier and the rf section. 5 rf in? complementary input to the rf prescaler. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 6 rf in+ input to the rf prescaler. this small signal input is ac-coupled to the external vco. 7 av dd 1 power supply pin for the rf section. nominally 3 v. a 100 pf decoupling capacitor to the ground plane should be placed as close as possible to this pin. 8 dv dd 1 power supply pin for the n divider. should be the same voltage as av dd 1. a 0.1 f decoupling capacitor to ground should be placed as close as possible to this pin. 9 d gnd 1 ground return pin for dv dd 1. 10 dv dd 2 power supply pin for the ref in buffer and r divider. nominally 3 v. a 0.1 f decoupling capacitor to ground should be placed as close as possible to this pin. 11 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k (see figure 15 ). this input can be driven from a ttl or cmos crystal oscillator or it can be ac-coupled. 12 d gnd 2 ground return pin for dv dd 2 and dv dd 3. 13 dv dd 3 power supply pin for the serial interface logic. nominally 3 v. 14 sd gnd ground return pin for the - modulator. 15 sdv dd power supply pin for the digital - modulator. nominally 3 v. a 0.1 f decoupling capacitor to the ground plane should be placed as close as possible to this pin. 16 mux out multiplexer output. this multiplexer o utput allows either the lock detect, th e scaled rf, or the scaled reference frequency to be accessed externally (see figure 35 ). 17 clk serial clock input. data is clocked in to the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 18 data serial data input. the serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 19 le load enable, cmos input. when le goes high, the data stored in the shift register is loaded into the register that is selected by the three lsbs. 20 v p 1 power supply pin for the phase frequency detector (pfd). nominally 5 v, should be at the same voltage at v p 2. a 0.1 f decoupling capacitor to ground should be placed as close as possible to this pin. 21 d gnd 3 ground return pin for v p 1. 22 a gnd 2 ground return pin for v p 2.
adf4193 rev. b | page 7 of 28 pin no. mnemonic description 23 r set connecting a resistor between this pin and gnd sets the ch arge pump output current. the nominal voltage bias at the r set pin is 0.55 v. the relationship between i cp and r set is i cp = 0.25/ r set so, with r set = 2.4 k, i cp = 104 a. 24 v p 2 power supply pin for the charge pump. nominally 5 v, should be at the same voltage at v p 1. a 0.1 f decoupling capacitor to ground should be placed as close as possible to this pin. 25 ain? differential amplifiers negative input pin. 26 cp out? differential charge pumps negative output pin. should be connected to ain? and the loop filter. 27 sw2 fast lock switch 2. this switch is closed to sw gnd while the sw1/2 timeout counter is active. 28 sw gnd common for sw1 and sw2 switches. should be connected to the ground plane. 29 sw1 fast lock switch 1. this switch is closed to sw gnd while the sw1/2 timeout counter is active. 30 cp out+ differential charge pumps positive output pin. should be connected to ain+ and the loop filter. 31 ain+ differential amplifiers positive input pin. 32 v p 3 power supply pin for the differential amplifier. this can rang e from 5.0 v to 5.5 v. a 0.1 f decoupling capacitor to ground should be placed as close as possible to this pi n. also requires a 10 f decoupling capacitor to ground.
adf4193 rev. b | page 8 of 28 typical performance characteristics 05328-038 freq. unit ghz keyword r param type s impedance 50 data format ma freq. mags11 angs11 0.5 0.8897 ?16.6691 0.6 0.87693 ?19.9279 0.7 0.85834 ?23.561 0.8 0.85044 ?26.9578 0.9 0.83494 ?30.8201 1.0 0.81718 ?34.9499 1.1 0.80229 ?39.0436 1.2 0.78917 ?42.3623 1.3 0.77598 ?46.322 1.4 0.75578 ?50.3484 1.5 0.74437 ?54.3545 1.6 0.73821 ?57.3785 1.7 0.7253 ?60.695 1.8 0.71365 ?63.9152 1.9 0.70699 ?66.4365 2.0 0.7038 ?68.4453 2.1 0.69284 ?70.7986 2.2 0.67717 ?73.7038 freq. mags11 angs11 2.3 0.67107 ?75.8206 2.4 0.66556 ?77.6851 2.5 0.6564 ?80.3101 2.6 0.6333 ?82.5082 2.7 0.61406 ?85.5623 2.8 0.5977 ?87.3513 2.9 0.5655 ?89.7605 3.0 0.5428 ?93.0239 3.1 0.51733 ?95.9754 3.2 0.49909 ?99.1291 3.3 0.47309 ?102.208 3.4 0.45694 ?106.794 3.5 0.44698 ?111.659 3.6 0.43589 ?117.986 3.7 0.42472 ?125.62 3.8 0.41175 ?133.291 3.9 0.41055 ?140.585 4.0 0.40983 ?147.97 figure 4. s parameter data for the rf input 05328-006 frequency (hz) phase noise (dbc/hz) 1k 10k 100k 1m 10m ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 100m gsm900 rx setup, 40khz loop bw, dither off rf = 1092.8mhz, f ref = 26mhz, mod = 130 n = 42 4/130 integer boundary spur: ?103dbc @ 800khz figure 5. ssb phase noise plot at 1092.8 mhz (gsm900 rx setup) vs. free running vco noise 05328-010 frequency (mhz) spur level (dbc) 1846 1859 ?120 ?110 ?100 ?90 ?80 ?70 ?60 1872 400khz spurs @ 25 c 400khz spurs @ 85 c dcs1800 tx setup with dither off, 60khz loop bw, 13mhz pfd. measured on eval-adf4193-eb1 board figure 6. 400 khz fractional spur levels across all dcs1800 tx channels over two-integer multiples of the pfd reference 05328-005 rf in frequency (mhz) rf in level (dbm) 0 1000 2000 3000 4000 ?35 0 ?5 ?10 ?15 ?20 ?25 ?30 5000 4/5 prescaler 8/9 prescaler figure 7. rf input sensitivity 05328-007 frequency (hz) phase noise (dbc/hz) 1k 10k 100k 1m 10m ?170 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 100m dcs1800 tx setup, 60khz loop bw, dither off rf = 1842.6mhz, f ref = 13mhz, mod = 65 dsb integrated phase error = 0.46 rms sirenza 1843t vco figure 8. ssb phase noise plot at 1842.6 mhz (dcs1800 tx setup) 05328-011 frequency (mhz) spur level (dbc) 1846 1859 ?120 ?110 ?100 ?90 ?80 ?70 ?60 1872 600khz spurs @ 25 c 600khz spurs @ 85 c dcs1800 tx setup with dither off, 60khz loop bw, 13mhz pfd. measured on eval-adf4193-eb1 board figure 9. 600 khz fractional spur levels across all dcs1800 tx channels over two-integer multiples of the pfd reference
adf4193 rev. b | page 9 of 28 05328-040 time ( s) (v) ?1 0 1 2 3 4 5 9876543210 v tune cp out+ cp out? dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193-eb1 evaluation board. timers: icp = 28, sw1/sw2, sw3 = 35. frequency lock in wide bw mode @ 4 s. figure 10. v tune settling transient for a 75 mhz jump from 1818 mhz to 1893 mhz with sirenza 1843t vco 05328-008 time ( s) phase error (degrees) ?5 0 5 10 15 20 25 30 35 40 ?50 50 40 30 20 10 0 ?10 ?20 ?30 ?40 45 +25 c +85 c ?40 c dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193-eb1 evaluation board with ad8302 phase detector. timers: icp = 28, sw1/sw2, sw3 = 35. peak phase error < 5 @ 17.8 s figure 11. phase settling transient for a 75 mhz jump from 1818 mhz to 1893 mhz (v tune 1.8 v to 3.7 v with sirenza 1843t vco) 05328-012 cp out + / cp out ? voltage (v) i cp (ma) mismatch (%) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 ?8 ?6 ?4 ?2 0 2 4 6 8 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 5.0 icp out + p, icp out ? p charge pump mismatch (%) normal operating range icp out + n, icp out ? n i up = | icp out + p | + | icp out ? n | i down = | icp out ? p | + | icp out + n | figure 12. differential charge pump output compliance range and charge pump mismatch with v p 1 = v p 2 = 5 v 05328-041 time ( s) (v) ?1 0 1 2 3 4 5 9876543210 v tune cp out? cp out+ dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193-eb1 evaluation board. timers: icp = 28, sw1/sw2, sw3 = 35. frequency lock in wide bw mode @ 5 s. figure 13. v tune settling transient for a 75 mhz jump down from 1893 mhz to 1818 mhz, the bottom of the allowed tuning range with the sirenza 1843t vco 05328-009 time ( s) phase error (degrees) ?5 0 5 10 15 20 25 30 35 40 ?50 50 40 30 20 10 0 ?10 ?20 ?30 ?40 45 +25 c +85 c ?40 c dcs1800 tx setup, 60khz loop bw. measured on eval-adf4193-eb1 evaluation board with ad8302 phase detector. timers: icp = 28, sw1/sw2, sw3 = 35. peak phase error < 5 @ 19.2 s figure 14. phase settling transient for a 75 mhz jump from 1893 mhz to 1818 mhz (v tune = 3.7 v to 1.8 v with sirenza 1843t vco) 05328-013 frequency (mhz) (v) 1780 1800 1820 1840 1860 1880 1900 1920 1940 0 2 1 3 4 5 v p 1 = v p 2 = 5v v p 3 = 5.5v v cmr = 3.3v cp out? (= ain?) a out (= v tune ) cp out+ (= ain+) figure 15. tuning range with a sirenza 1843t vco and a 5.5 v differential amplifier power supply voltage
adf4193 rev. b | page 10 of 28 05328-042 frequency (hz) noise (nv/ hz) 1k 10k 100k 1m 1 10 100 1000 10m 7nv/ hz @ 20khz figure 16. voltage noise density measured at the differential amplifier output 05328-014 drain voltage (v) r on ( ? ) 01234 0 100 70 90 80 60 50 40 30 20 10 5 +85c sw3 ?40c +25c ?40c +25c +85c sw1/ sw2 tuning voltage range figure 17. on resistance of loop filter switches sw1/sw2 and sw3 05328-044 phase code phase detector output (v) 0 0 1.8 1.5 1.2 0.9 0.6 0.3 13011710491786552392613 measured using ad8302 phase detector y-axis scale: 10mv/degree rf = 1880mhz, pfd = 26mhz, mod = 130 x-axis scale: 2.77 q /step figure 18. detected rf output phase for phase code sweep from 0 to mod 05328-045 interval between r0 writes should be a multiple of mod reference cycles (5s) for coherent phase measurements agilent hp8663a sig. gen. tektronix tds714l oscilloscope adf4193 eval board 104mhz 5dbm 10mhz ext ref 1880mhz 1805 1880mhz rf out ref in r&s smt03 sig. gen. inpa ad8302 evb vphs inpb figure 19. test setup for phase lock time measurement
adf4193 rev. b | page 11 of 28 theory of operation the adf4193 is targeted at gsm base station requirements, specifically to eliminate the need for ping-pong solutions. it works based on fast lock, using a wide loop bandwidth during a frequency change and narrowing the loop bandwidth once frequency lock is achieved. widening the loop bandwidth is achieved by increasing the charge pump current. switches are included to change the loop filter component values to maintain stability with the changing charge pump current. the narrow loop bandwidth ensures that phase noise and spur specifications are met. a differential charge pump and loop filter topology are used to ensure that the fast lock time benefit from widening the loop bandwidth is maintained when the loop is restored to narrow bandwidth mode for normal operation. reference input section the reference input stage is shown in figure 20 . switches s1 and s2 are normally closed, and s3 is normally open. during power- down, s3 is closed, and s1 and s2 are opened to ensure that there is no loading of the ref in pin. the falling edge of ref in is the active edge at the positive edge triggered pfd. 05328-016 buffer to r counter ref in 100k nc s2 s3 no nc s1 power-down control figure 20. reference input stage r counter and doubler the 4-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). a toggle flip-flop can be optionally inserted after the r counter to give a further divide-by-2. using this option has the additional advantage of ensuring that the pfd reference clock has a 50/50 mark-space ratio. this ratio gives the maximum separation between the fast lock timer clock, which is generated off the falling edge of the pfd reference, and the rising edge, which is the active edge in the pfd. it is recommended that this toggle flip-flop be enabled for all even r divide values greater than 2. it must be enabled if dividing down a ref in frequency that is greater than 120 mhz. an optional doubler before the 4-bit r counter can be used for low ref in frequencies, up to 20 mhz. with these programmable options, reference division rati os from 0.5 to 30 between ref in and the pfd are possible. rf input stage the rf input stage is shown in figure 21 . it is followed by a 2-stage limiting amplifier to generate the cml clock levels needed for the prescaler. two prescaler options are selectable: a 4/5 and an 8/9. the 8/9 prescaler is selected for n divider values greater than 80. 05328-017 bias generator 1.6v agnd av dd 500 500 rf in? rf in+ figure 21. rf input stage rf n divider the rf n divider allows a fractional division ratio in the pll feedback path. the integer and fractional parts of the division are programmed using separate registers, as shown in figure 22 and described in the int, frac, and mod relationship section. integer division ratios from 26 to 255 are allowed and a third-order, - modulator interpolates the fractional value between the integer steps. 05328-018 third-order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from rf input stage to pf d n counter figure 22. fractional-n divider int, frac, and mod relationship the int, frac, and mod values, programmed through the serial interface, make it possible to generate rf output frequencies that are spaced by fractions of the pfd reference frequency. the n divider value, shown inside the brackets of the following equation for the rf vco frequency (rf out ), is made up of an integer part (int) and a fractional part (frac/mod): rf out = f pfd [ int + ( frac / mod )] where: rf out is the output frequency of the external vco. f pfd is the pfd reference frequency.
adf4193 rev. b | page 12 of 28 the value of mod is chosen to give the desired channel step with the available reference frequency. thereafter, program the int and frac words for the desired rf output frequency. see the worke d e x ample section for more information. pfd and charge pump the pfd takes inputs from the r divider and n divider and produces up and down outputs with a pulse width difference proportional to the phase difference between the inputs. the charge pump outputs a net up or down current pulse of a width equal to this difference, to pump up or pump down the voltage that is integrated onto the loop filter, which in turn increases or decreases the vco output frequency. if the n divider phase lags the r divider phase, a net up current pulse is produced that increases the vco frequency (and thus the phase). if the n divider phase leads the r divider edge, then a net down pulse is produced to reduce the vco frequency and phase. figure 23 is a simplified schematic of the pfd and charge pump. the charge pump is made up of an array of 64 identical cells, each of which is fully differential. all 64 cells are active during fast lock, but only one is active during normal operation. because a single-ended control voltage is required to tune the vco, an on-chip, differential-to-single-ended amplifier is provided for this purpose. in addition, because the phase-lock loop only controls the differential voltage generated across the charge pump outputs, an internal common-mode feedback (cmfb) loop biases the charge pump outputs at a common-mode voltage of approximately 2 v. 05328-019 clr qd r divider n divider charge pump array [64:1] cmfb en[64:1] clr qd cp out+ cp out? figure 23. pfd and differential charge pump simplified schematic differential charge pump the charge pump cell (see figure 24 ) has a fully differential design for best up-to-down current matching. good matching is essential to minimize the phase offset created when switching the charge pump current from its high value (in fast lock mode) to its nominal value (in normal mode). to pump up, the up switches are on and pmos current is sourced out through cp out+ ; this increases the voltage on the external loop filter capacitors connected to cp out+ . similarly, the nmos current sink on cp out? decreases the voltage on the external loop filter capacitors connected to cp out? . therefore, the differential voltage between cp out+ and cp out? increases. to pump down, pmos current sources out through cp out? and nmos current sinks in through cp out+ , which decreases the (cp out+ , cp out? ) differential voltage. the charge pump up/ down matching is improved by an order of magnitude over the conventional single-ended charge pump that depended on the matching of two different device types. the up/down matching in this structure depends on how a pmos matches a pmos and an nmos matches an nmos. 05328-035 v bias p pp nn up down down up v bias n cp out+ c pout? figure 24. differential charge pump cell with external loop filter components fast lock timeout counters timeout counters, clocked at one quarter the pfd reference frequency, are provided to precisely control the fast locking operation (see figure 25 ). whenever a new frequency is programmed, the fast lock timers start and the pll locks into wide bw mode with the 64 identical 100 a charge pump cells active (6.4 ma total). when the icp counter times out, the charge pump current is reduced to 1 by deselecting cells in binary steps over the next six timer clock cycles, until just one 100 a cell is active. the charge pump current switching from 6.4 ma to 100 a equates to an 8-to-1 change in loop band- width. the loop filter must be changed to ensure stability when this happens. that is the job of the sw1, sw2, and sw3 switches. the application circuit (shown in figure 36 ) shows how they can be used to reconfigure the loop filter time constants. the application circuits close to short out external loop filter resistors during fast lock and open when their counters time out to restore the filter time constants to their normal values for the 100 a charge pump current. because it takes six timer clock cycles to reduce the charge pump current to 1, it is recommended that both switch timers be programmed to the value of the icp timer + 7.
adf4193 rev. b | page 13 of 28 05328-036 sw1/sw2 timeout counter sw3 timeout counter icp timeout counter en[64:1] 4 start f pfd sw3 a out sw2 sw gnd sw1 write to r0 charge pump enable logic figure 25. fast lock timeout counters differential amplifier the internal, low noise, differential-to-single-ended amplifier is used to convert the differential charge pump output to a single- ended control voltage for the tuning port of the vco. figure 26 shows a simplified schematic of the differential amplifier. the output voltage is equal to the differential voltage, offset by the voltage on the cmr pin, according to v aout = ( v ain+ ? v ain? ) + v cmr the cmr offset voltage is internally biased to three-fifths of v p 3, the differential amplifier power supply voltage, as shown in figure 26 . connect a 0.1 f capacitor to ground to the cmr pin to roll off the thermal noise of the biasing resistors. as can be seen in figure 15 , the differential amplifier output voltage behaves according to the previous equation over a 4 v range from approximately 1.2 v minimum up to v p 3 ? 0.3 v. however, fast settling is guaranteed only over a tuning voltage range from 1.8 v up to v p 3 ? 0.8 v. this is to allow sufficient room for overshoot in the pll frequency settling transient. noise from the differential amplifier is suppressed inside the pll bandwidth. for loop bandwidths >20 khz, the 1/f noise has a negligible effect on the pll output phase noise. outside the loop bandwidth, the differential amplifiers noise fm modulates the vco. the passive filter network following the differential amplifier, shown in figure 36 , suppresses this noise contribution to below the vco noise from offsets of 400 khz and above. this network has a negligible effect on lock time because it is bypassed when sw3 is closed while the loop is locking. 05328-020 a in? aout a in+ cmr v p 3 c ext = 0.1f 20k? 30k? 500? 500 ? 500? 500 ? figure 26. differential amplifier block diagram mux out and lock detect the output multiplexer on the adf4193 allows the user to access various internal points on the chip. the state of mux out is controlled by m4 to m1 in the mux register. figure 35 shows the full truth table. figure 27 shows the mux out section in block diagram form. 05328-021 r divider output n divider output serial data output d gnd dv dd control mux mux out logic low three-state output timer outputs digital lock detect logic high note: not all muxout modes shown refer to mux register figure 27. mux out circuit lock detect mux out can be programmed to provide a digital lock detect signal. digital lock detect is active high. its output goes high if there are 40 successive pfd cycles with an input error of less than 3 ns. for reliable lock detect operation with rf frequencies <2 ghz, it is recommended that this threshold be increased to 10 ns by programming register r6. the digital lock detect goes low again when a new channel is programmed or when the error at the pfd input exceeds 30 ns for one or more cycles. input shift register the adf4193 serial interface section includes a 24-bit input shift register. data is clocked in msb first on each rising edge of clk. data from the shift register is latched into one of eight control registers, r0 to r7, on the rising edge of latch enable (le). the destination register is determined by the state of the three control bits (control bit c3, control bit c2, and control bit c1) in the shift register. the three lsbs are bit db2, bit db1, and bit db0, as shown in the timing diagram of figure 2 . the truth table for these bits is shown in table 5 . figure 28 shows a summary of how the registers are programmed. table 5. c3, c2, and c1 truth table control bits c3 c2 c1 ame reister 0 0 0 frac/int r0 0 0 1 mod/r r1 0 1 0 phase r2 0 1 1 function r3 1 0 0 charge pump r4 1 0 1 power-down r5 1 1 0 mux r6 1 1 1 test mode r7
adf4193 rev. b | page 14 of 28 register map 05328-022 db23 f5 db22 f4 db21 0 db20 f2 db19 f1 db18 r4 db17 r3 db16 r2 db15 r1 db14 m12 db13 m11 db12 m10 db11 m9 db10 m8 db9 m7 db8 m6 db7 m5 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (0) db1 c2 (0) db0 c1 (1) dbb dbb dbb dbb dbb 4-bit rf r counter cp adj ref/2 reserved prescaler doubler enable 12-bit modulus control bits mod/r register (r1) db15 0 db14 p12 db13 p11 db12 p10 db11 p9 db10 p8 db9 p7 db8 p6 db7 p5 db6 p4 db5 p3 db4 p2 db3 p1 db2 c3 (0) db1 c2 (1) db0 c1 (0) dbb reserved 12-bit phase control bits phase register (r2) db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 1 db5 f3 db4 1 db3 f1 db2 c3 (0) db1 c2 (1) db0 c1 (1) pfd polarity reserved cpo gnd reserved control bits function register (r3) db15 m13 db14 m12 db13 m11 db12 m10 db11 0 db10 0 db9 0 db8 0 db7 0 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (1) db1 c2 (1) db0 c1 (0) reserved mux out control bits sigma-delta and lock detect modes mux register (r6) db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 0 db5 0 db4 0 db3 0 db2 c3 (1) db1 c2 (1) db0 c1 (1) reserved control bits test mode register (r7) db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (1) counter reset cp 3-state pd charge pump pd diff amp control bits power-down register (r5) db23 0 db22 0 db21 0 db20 0 db19 0 db18 0 db17 0 db16 0 db15 0 db14 1 db13 c9 db12 c8 db11 c7 db10 c6 db9 c5 db8 c4 db7 c3 db6 c2 db5 c1 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (0) 9-bit timeout counter reserved control bits timer select charge pump register (r4) dbb = double buffered bit(s) db23 0 db22 n8 db21 n7 db20 n6 db19 n5 db18 n4 db17 n3 db16 n2 db15 n1 db14 f12 db13 f11 db12 f10 db11 f9 db10 f8 db9 f7 db8 f6 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (0) db1 c2 (0) db0 c1 (0) 8-bit rf int value 12-bit rf frac value control bits frac/int register (r0) reserved figure 28. register map
adf4193 rev. b | page 15 of 28 frac/int register (r0) 05328-023 db23 reserved 0 db22 n8 db21 n7 db20 n6 db19 n5 db18 n4 db17 n3 db16 n2 db15 n1 db14 f12 db13 f11 db12 f10 db11 f9 db10 f8 db9 f7 db8 f6 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (0) db1 c2 (0) db0 c1 (0) 8-bit rf int value 12-bit rf frac value control bits f12 0 0 0 0 . . . 1 1 1 1 f11 0 0 0 0 . . . 1 1 1 1 f10 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... f3 0 0 0 0 . . . 1 1 1 1 f2 0 0 1 1 . . . 0 0 1 1 f1 0 1 0 1 . . . 0 1 0 1 fractional value (frac) 0 1 2 3 . . . 4092 4093 4094 4095 n8 0 . . . 1 n7 0 . . . 1 n6 0 . . . 1 n5 1 . . . 1 n4 1 . . . 1 n3 0 . . . 1 n2 1 . . . 1 n1 0 . . . 1 integer value (int) 26 . . . 255 0 = < frac < mod figure 29. frac/int register (r0) r0, the frac/int register, is used to program the synthesizer output frequency. on the next pfd cycle following a write to r0, the n divider section is updated with the new int and frac values. at the same time, the pll automatically enters fast lock mode and the charge pump current is increased to its maximum value and stays at this value until the icp timeout counter times out, and switches sw1, sw2, and sw3 closed and remains closed until the sw1, sw2, and sw3 timeout counters time out. once all registers are programmed during the initialization sequence (see table 8 ), all that is required thereafter to program a new channel is a write to r0. however, as described in the programming section, it can also be desirable to program r1 and r2 register settings on a channel-by-channel basis. these settings are double buffered by the write to r0. this means that while the data is loaded through the serial interface on the respective r1 and r2 write cycles, the synthesizer is not updated with their data until the next write to register r0. control bits the three lsbs, control bit c3, co ntrol bit c2, and control bit c1, should be set to 0, 0, 0, respectively, to select r0, the frac/int register. reserved bit bit db23 is reserved and must be set to 0. 8-bit int value these eight bits set the int value, which determines the integer part of the feedback division factor. all integer values from 26 to 255 are allowed. see the wor ke d e x ample section. 12-bit frac value the 12 frac bits set the numerator of the fraction that is input to the - modulator. this, along with int, specifies the new frequency channel that the synthesizer locks to, as shown in the worke d e x ampl e section. frac values from 0 to mod ? 1 cover channels over a frequency range equal to the pfd reference frequency.
adf4193 rev. b | page 16 of 28 mod/r register (r1) 05328-024 db23 f5 db22 f4 db21 0 db20 f2 db19 f1 db18 r4 db17 r3 db16 r2 db15 r1 db14 m12 db13 m11 db12 m10 db11 m9 db10 m8 db9 m7 db8 m6 db7 m5 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (0) db1 c2 (0) db0 c1 (1) 4-bit rf r counter cp adj ref/2 reserved prescaler doubler enable 12-bit modulus control bits 0 1 nominal adjusted cp adj f5 0 1 disable enable ref/2 f4 0 1 f2 4/5 8/9 prescaler 0 1 f1 doubler disabled doubler enabled doubler enable m12 0 0 0 . . . 1 1 1 1 m11 0 0 0 . . . 1 1 1 1 m10 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... m3 1 1 1 . . . 1 1 1 1 m2 0 1 1 . . . 0 0 1 1 m1 1 0 1 . . . 0 1 0 1 interpolator modulus value (mod) 13 14 15 . . . 4092 4093 4094 4095 r4 0 0 0 0 . . . 1 1 1 1 r3 0 0 0 1 . . . 1 1 1 1 r2 0 1 1 0 . . . 0 0 1 1 r1 1 0 1 0 . . . 0 1 0 1 rf r counter divide ratio 1 2 3 4 . . . 12 13 14 15 figure 30. mod/r register (r1) this register is used to set the pfd reference frequency and the channel step size, which is determined by the pfd frequency divided by the fractional modulus. note that the mod, r counter, ref/2, cp adj, and doubler enable bits are double buffered. they do not take effect until the next write to r0 (frac/int register) is complete. control bits with c3, c2, and c1 set to 0, 0, 1, respectively, the mod/r register (r1) is programmed. cp adj when this bit is set to 1, the charge pump current is scaled up 25% from its nominal value on the next write to r0. when this bit is set to 0, the charge pump current stays at its nominal value on the next write to r0. see the programming section for more information on how this feature can be used. ref/2 setting this bit to 1 inserts a divide-by-2, toggle flip-flop between the r counter and pfd, which extends the maximum ref in input rate. reserved bit reserved bit db21 must be set to 0. doubler enable setting this bit to 1 inserts a frequency doubler between ref in and the 4-bit r counter. setting this bit to 0 bypasses the doubler. 4-bit rf r counter it allows the ref in frequency to be divided down to produce the reference clock to the pfd. all integer values from 1 to 15 are allowed. see the worke d e x ample section. 12-bit interpolator modulus for a given pfd reference frequency, the fractional denomina- tor or modulus sets the channel step resolution at the rf output. all integer values from 13 to 4095 are allowed. see the programming section for additional information and guidelines for selecting the value of mod.
adf4193 rev. b | page 17 of 28 phase register (r2) 05328-025 db15 0 db14 p12 db13 p11 db12 p10 db11 p9 db10 p8 db9 p7 db8 p6 db7 p5 db6 p4 db5 p3 db4 p2 db3 p1 db2 c3 (0) db1 c2 (1) db0 c1 (0) reserved 12-bit phase control bits p12 0 0 0 . . . 1 1 1 1 p11 0 0 0 . . . 1 1 1 1 p10 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... p3 0 0 0 . . . 1 1 1 1 p2 0 0 1 . . . 0 0 1 1 p1 0 1 0 . . . 0 1 0 1 phase value 1 0 1 2 . . . 4092 4093 4094 4095 1 0 = < phase value < mod figure 31. phase register (r2) 12-bit phase the phase word sets the seed value of the - modulator. it can be programmed to any integer value from 0 to mod. as the phase word is swept from 0 to mod, the phase of the vco output sweeps over a 360 range in steps of 360/mod. note that the phase bits are double buffered. they do not take effect until the le of the next write to r0 (frac/int register). therefore, if it is desired to change the phase of the vco output frequency, it is necessary to rewrite the int and frac values to r0, following the write to r2. the output of a fractional-n pll can settle to any one of the mod possible phase offsets with respect to the reference, where mod is the fractional modulus. if it is desired to keep the output at the same phase offset with respect to the reference, each time that particular output frequency is programmed, then the interval between writes to r0 must be an integer multiple of mod reference cycles. if it is desired to keep the outputs of two adf4193-based synthesizers phase coherent with each other, but not necessarily with their common reference, then it is only required to ensure that the write to r0 on both chips is performed during the same reference cycle. the interval between r0 writes in this case does not have to be an integer multiple of the mod cycles. reserved bit the reserved bit, bit db15, should be set to 0.
adf4193 rev. b | page 18 of 28 function register (r3) 05328-026 db15 0 db14 0 db13 0 db12 0 db11 0 db10 0 db9 0 db8 0 db7 0 db6 1 db5 f3 db4 1 db3 f1 db2 c3 (0) db1 c2 (1) db0 c1 (1) pfd polarity reserved cpo gnd reserved control bits 0 1 f1 negative positive pfd polarity 0 1 f3 cpo/cpo gnd normal cpo gnd figure 32. function register (r3) r3, the function register (c3, c2, c1 set to 0, 1, 1, respectively), only needs to be programmed during the initialization sequence (see table 8 ). cpo gnd when the cpo gnd bit is low, the charge pump outputs are internally pulled to ground. this is invoked during the initialization sequence to discharge the loop filter capacitors. for normal operation, this bit should be high. pfd polarity this bit should be set to 1 for positive polarity and set to 0 for negative polarity. reserved bits the bit db15 to bit db6 are reserved bits and should be programmed to hex code 001, and reserved bit db4 should be set to 1.
adf4193 rev. b | page 19 of 28 charge pump register (r4) 05328-027 db23 0 db22 0 db21 0 db20 0 db19 0 db18 0 db17 0 db16 0 db15 0 db14 1 db13 c9 db12 c8 db11 c7 db10 c6 db9 c5 db8 c4 db7 c3 db6 c2 db5 c1 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (0) 9-bit timeout counter reserved control bits timer select 0 0 1 1 f2 0 1 0 1 f1 sw1/sw2 sw3 icp not used timer select c9 0 0 0 0 . . . 1 1 1 1 c8 0 0 0 0 . . . 1 1 1 1 c7 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... c3 0 0 0 0 . . . 1 1 1 1 c2 0 0 1 1 . . . 0 0 1 1 c1 0 1 0 1 . . . 0 1 0 1 timeout counter 0 1 2 3 . . . 508 509 510 511 xpfd cycles 0 4 8 12 . . . 2032 2036 2040 2044 delay s 1 0 0.15 0.30 0.46 . . . 78.15 78.30 78.46 78.61 1 delay with 26mhz pfd figure 33. charge pump register (r4) reserved bits bit db23 to bit db14 are reserved and should be set to hex code 001 for normal operation. 9-bit timeout counter these bits are used to program the fast lock timeout counters. the counters are clocked at one-quarter the pfd reference frequency, therefore, their time delay scales with the pfd frequency according to delay ( s ) = ( timeout counter value 4)/( pfd frequency ) for example, if 35 were loaded with timer select (00) with a 13 mhz pfd, then sw1/sw2 would be switched after (35 4)/13 mhz = 10.8 s timer select these two address bits select the timeout counter to be programmed. note that to set up the adf4193 correctly requires setup of these three timeout counters; therefore, three writes to this register are requir ed in the initialization sequence. table 6 shows example values for a gsm tx synthesizer with a 60 khz final loop bw. see the applications section for more information. table 6. recommended values for a gsm tx lo timer select timeout counter value time (s) with pfd = 13 mhz 10 icp 28 8.6 01 sw1/2 35 10.8 00 sw3 35 10.8 on each write to r0, the timeout counters start. switch sw3 closes until the sw3 counter times out. similarly, switches sw1/sw2 close until the sw1/sw2 counter times out. when the icp counter times out, the charge pump current is ramped down from 64 to 1 in six binary steps. it is recommended that the sw1, sw2, and sw3 timeout counter values are set equal to the icp timeout counter value plus 7, as in the example of tabl e 6 .
adf4193 rev. b | page 20 of 28 power-down register (r5) 05328-028 db7 f5 db6 f4 db5 f3 db4 f2 db3 f1 db2 c3 (1) db1 c2 (0) db0 c1 (1) counter reset cp 3-state pd charge pump control bits pd diff amp 0 1 f4 0 1 f5 disabled enabled diff amp power-down 0 1 f2 normal operation 3-state enabled charge pump 3-state 0 1 f1 normal operation counter reset counter reset 0 1 f3 disabled enabled charge pump power-down figure 34. power-down register (r5) r5, the power-down register (c3, c2, c1 set to 1, 0, 1, respectively) can be used to software power down the pll and differential amplifier sections. after power is initially applied, there must be writes to r5 to clear the power-down bits and to r2, r1, and r0 before the adf4193 comes out of power-down. power-down differential amplifier when bit db6 and bit db7 are set high, the differential amplifier is put into power-down. when bit db6 and bit db7 are set low, normal operation is resumed. power-down charge pump setting bit db5 high activates a charge pump power-down and the following events occur: ? all active dc current paths are removed, except for the differential amplifier. ? the r and n divider counters are forced to their load state conditions. ? the charge pump is powered down with its outputs in three- state mode. ? the digital lock detect circuitry is reset. ? the rf in input is debiased. ? the reference input buffer circuitry is disabled. ? the serial interface remains active and capable of loading and latching data. for normal operation, bit db5 should be set to 0, followed by a write to r0. cp three-state when this bit is set high, the charge pump outputs are put into three-state. with the bit set low, the charge pump outputs are enabled. counter reset when this bit is set to 1, the counters are held in reset. for normal operation, this bit should be 0, followed by a write to r0.
adf4193 rev. b | page 21 of 28 mux register (r6) 05328-029 db15 m13 db14 m12 db13 m11 db12 m10 db11 0 db10 0 db9 0 db8 0 db7 0 db6 m4 db5 m3 db4 m2 db3 m1 db2 c3 (1) db1 c2 (1) db0 c1 (0) reserved mux out control bits sigma-delta and lock detect modes 0 1 1 m10 0 1 0 m11 0 0 0 all other states m12 0 0 1 m13 init state, dither off, 3ns lock detect threshold dither on 10ns lock detect threshold reserved sigma-delta modes 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 m4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 m3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 m2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 m1 3-state digital lock detect n divider output logic high r counter reserved serial data out logic low r divider/2 output n divider/2 output reserved reserved icp timeout signal sw1/2 timeout signal sw3 timeout signal reserved mux out figure 35. mux register (r6) with c3, c2, and c1 set to 1, 1, 0, respectively, the mux register is programmed. - and lock detect modes bit db15 to bit db12 are used to reconfigure certain pll operating modes. in the initialization sequence after power is applied to the chip, the four bits must first be programmed to all zeros. this initializes the pll to a known state with dither off in the - modulator and a 3 ns pfd error threshold in the lock detect circuit. to turn on dither in the - modulator, an additional write should be made to register r6 to program bits [db15:db12] = [0011]. however, for lowest noise operation, it is best to leave dither off. to change the lock detect threshold from 3 ns to 10 ns, a separate write to r6 should be performed to program bits [db15:db12] = [1001]. this should be done for reliable lock detect operation when the rf frequency is <2 ghz. a write to r6 that programs bits [db15:db12] = [0000] returns operation to the default state with both dither off and a 3 ns lock detect threshold. reserved bits the reserved bits must all be set to 0 for normal operation. mux out modes these bits control the on-chip multiplexer. see figure 35 for the truth table. this pin is useful for diagnosis because it allows the user to look at various internal points of the chip, such as the r divider and int divider outputs. in addition, it is possible to monitor the programmed timeout counter intervals on mux out . for example, if the icp timeout counter was programmed to 65 (with a 26 mhz pfd), then following the next write to r0, a pulse width of 10 s would be observed on the mux out pin. digital lock detect is available via the mux out pin.
adf4193 rev. b | page 22 of 28 programming the adf4193 can synthesize output frequencies with a channel step or resolution that is a fraction of the input reference frequency. for a given input reference frequency and a desired output frequency step, the first choice to make is the pfd reference frequency and the mod. once these are chosen, the desired output frequency channels are set by programming the int and frac values. worked example in this example of a gsm900 rx system, it is required to generate rf output frequencies with channel steps of 200 khz. a 104 mhz reference frequency input (ref in ) is available. the r divider setting that set the pfd reference is shown in equation 1. f pfd = ref in [(1 + d )/( r (1 + t ))] (1) where: ref in is the input reference frequency. d is the doubler enable bit (0 or 1). r is the 4-bit r counter code (015). t is the ref/2 bit (0 or 1). the maximum pfd reference frequency of 26 mhz is chosen and the following settings are programmed to give an r divider value of 4: doubler enable = 0 r = 2 ref/2 = 1 next, the modulus is chosen to allow fractional steps of 200 khz. mod = 26 mhz/200 khz = 130 (2) once the channel step is defined, the following equation shows how output frequency channels are programmed: rf out = [ int + ( frac / mod ] [ f pfd ] (3) where: rf out is the desired rf output frequency. int is the integer part of the division. frac is the numerator part of the fractional division. mod is the modulus or denominator part of the fractional division. for example, the frequency channel at 962.4 mhz is synthesized by programming the following values: int = 37 frac = 2 spur mechanisms the fractional spurs , integer boundary spurs , and reference spurs sections describe the three different spur mechanisms that arise with a fractional-n synthesizer and how the adf4193 can be programmed to minimize them. fractional spurs the fractional interpolator in the adf4193 is a third-order, - modulator (sdm) with a modulus (mod) that is programmable to any integer value from 13 to 4095. if dither is enabled, then the minimum allowed value of mod is 50. the sdm is clocked at the pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod. with dither turned off, the quantization noise from the - modulator appears as fractional spurs. the interval between spurs is f pfd / l , where l is the repeat length of the code sequence in the digital - modulator. for the third-order modulator used in the adf4193, the repeat length depends on the value of mod, as shown in table 7 . tale 7. fractional spurs with dither off condition (dither off) repeat length spur interval if mod is divisible by 2, but not 3 2 mod channel step/2 if mod is divisible by 3, but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 otherwise mod channel step with dither enabled, the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this can degrade the in-band phase noise at the pll output by as much as 10 db. therefore, for the lowest noise, dither off is a better choice, particularly when the final loop bw is low enough to attenuate even the lowest frequency fractional spur. the wide loop bandwidth range available with the adf4193 makes this possible in most applications. integer boundary spurs another mechanism for fractional spur creation involves interactions between the rf vco frequency and the reference frequency. when these frequencies are not integer related, spur sidebands appear on the vco output spectrum at an offset frequency that corresponds to the beat note or difference frequency between an integer multiple of the reference and the vco frequency.
adf4193 rev. b | page 23 of 28 these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the refer- ence where the difference frequency can be inside the loop bandwidth, thus the name integer boundary spurs. the 8:1 loop bandwidth switching ratio of the adf4193 makes it possible to attenuate all spurs to sufficiently low levels for most applications. the final loop bw can be chosen to ensure that all spurs are far enough out of band while meeting the lock time requirements with the 8 bandwidth boost. the adf4193s programmable modulus and r divider can also be used to avoid integer boundary channels. this option is described in the avoiding integer boundary channels section. reference spurs reference spurs are generally not a problem in fractional-n synthesizers as the reference offset is far outside the loop bandwidth. however, any reference feedthrough mechanism that bypasses the loop can cause a problem. one such mechanism is feedthrough of low levels of on-chip reference switching noise out through the rf in pin back to the vco, resulting in reference spur levels as high as C90 dbc. these spurs can be suppressed below C110 dbc by inserting sufficient reverse isolation, for example, through an rf buffer between the vco and rf in pin. in addition, care should be taken in the pcb layout to ensure that the vco is well separated from the input reference to avoid a possible feedthrough path on the board. power-up initialization after applying power to the adf4193, a 14-step sequence is recommended, as described in table 8 . the divider and timer setting used in the example in table 8 is for a dcs1800 tx synthesizer with a 104 mhz ref in frequency. table 8. power-up initialization sequence step register bits hex codes description 1 r5 [7:0] fd set all power-down bits. 2 r3 [15:0] 005b pd polarity = 1, ground cp out+ / cp out C. wait 10 ms allow time for loop filter capacitors to discharge. 3 r7 [15:0] 0007 clear test modes. 4 r6 [15:0] 000e initialize pll modes, digital lock detect on mux out . 5 r6 [15:0] 900e 10 ns lock detect threshold, digital lock detect on mux out . 6 r4 [23:0] 004464 sw1/sw2 timer = 10.8 s. 7 r4 [23:0] 00446c sw3 timer = 10.8 s. 8 r4 [23:0] 004394 icp timer = 8.6 s. 9 r2 [15:0] 00d2 phase = 26. 10 r1 [23:0] 520209 8/9 prescaler, doubler disabled, r = 4, toggle ff on, mod = 65. 11 r0 [23:0] 480140 int = 144, frac = 40 for 1880 mhz output frequency. 12 r3 [15:0] 007b pd polarity = 1, release cp out +/ cp out C. 13 r5 [7:0] 05 clear all power-down bits. 14 r0 [23:0] 480140 int = 144, frac = 40 for 1880 mhz output frequency. the adf4193 powers up after step 13. it locks to the programmed channel frequency after step 14. changing the frequency of the pll and the phase look-up table once the adf4193 is initialized, a write to register r0 is all that is required to program a new output frequency. the n divider is updated with the values of int and frac on the next pfd cycle following the le edge that latches in the r0 word. however, the settling time and spurious performance of the synthesizer can be further optimized by modifying r1 and r2 register settings on a channel- by-channel basis. these settings are double buffered by the write to r0. this means that while the data is loaded in through the serial interface on the respective r1 and r2 write cycles, the synthesizer is not updated with their data until the next write to register r0. the r2 register can be used to digitally adjust the phase of the vco output relative to the reference edge. the phase can be adjusted over the full 360 range at rf with a resolution of 360/mod. in most frequency synthesizer applications, the actual phase offset of the vco output with respect to the reference is unknown and does not matter. in such applications, the phase adjustment capability of the r2 register can instead be used to optimize the settling time performance, as described in the phase look-up table section.
adf4193 rev. b | page 24 of 28 phase look-up table the adf4193s fast lock sequence is initiated following the write to register r0. the fast lock timers are programmed so that after the pll has settled in wide bw mode, the charge pump current is reduced and loop filter resistor switches are opened to reduce the loop bw. the reference cycle on which these events occur is determined by the values preprogrammed into the timeout counters. figure 10 and figure 13 show that the lock time to final phase is dominated by the phase swing that occurs when the bw is reduced. once the pll has settled to final frequency and phase, in wide bw mode, this phase swing is the same, regardless of the size of the synthesizers frequency jump. the amplitude of the phase swing is related to the current flowing through the loop filter zero resistors on the pfd reference cycle that the sw1/sw2 switches are opened. in an integer-n pll, this current is zero once the pll has settled. in a fractional-n pll, the current is zero on average but varies from one reference cycle to the next, depending on the quantization error sequence output from the digital - modulator. because the - modulator is all digital logic, clocked at the pfd reference rate, for a given value of mod, the actual quantization error on any given reference cycle is determined by the value of frac and the phase word that the modulator is seeded with, following the write to r0. by choosing an appropriate value of phase, corresponding to the value of frac, that is programmed on the next write to r0, the size of the error current on the pfd reference cycle the sw1/sw2 switches opened, and thus the phase swing that occurs when the bw is reduced can be minimized. with dither off, the fractional spur pattern due to the sdms quantization noise also depends on the phase word the modulator is seeded with. tables of optimized frac and phase values for popular sw1/sw2 and icp timer settings can be down-loaded from the adf4193 product page. if making use of a phase table, first write phase to double buffered register r2, then write the int and frac to r0. avoiding integer boundary channels a further option when programming a new frequency involves a write to register r1 to avoid integer boundary spurs. if it is found that the integer boundary spur level is too high, an option is to move the integer boundary away from the desired channel by reprogramming the r divider to select a different pfd frequency. for example, if ref in = 104 mhz and r = 4 for a 26 mhz pfd reference and mod = 130 for 200 khz steps, the frequency channel at 910.2 mhz has a 200 khz integer boundary spur because it is 200 khz offset from 35 26 mhz. an alternative way to synthesize this channel is to set r = 5 for a 20.8 mhz pfd reference and mod = 104 for 200 khz steps. the 910.2 mhz channel is now 5 mhz offset from the nearest integer multiple of 20.8 mhz and the 5 mhz beat note spurs are well attenuated by the loop. setting double buffered bit r1 [23] = 1 (cp adj bit) increases the charge pump current by 25%, which compensates for the 25% increase in n with the change to the 20.8 mhz pfd frequency. this maintains constant loop dynamics and settling time performance for jumps between the two pfd frequencies. the cp adj bit should be cleared again when jumping back to 26 mhz-based channels. the register r1 settings necessary for integer boundary spur avoidance are all double buffered and do not become active on the chip until the next write to register r0. register r0 should always be the last register written to when programming a new frequency. serial interface activity the serial interface activity when programming the r2 or r1 registers causes no noticeable disturbance to the synthesizers settled phase or degradation in its frequency spectrum. therefore, in a gsm application, it can be performed during the active part of the data burst. because it takes just 10.2 s to program the three registers, r2, r1, and r0, with the 6.5 mhz serial interface clock rate typically used, this programming can also be performed during the previous guard period with the le edge to latch in the r0 data delayed until its time to switch frequency.
adf4193 rev. b | page 25 of 28 applications local oscillator for a gsm base station figure 36 shows the adf4193 being used with a vco to produce the lo for a gsm1800 base station. for gsm, the ref in signal can be any integer multiple of 13 mhz, but the main requirement is that the slew rate is at least 300 v/s. the 5 dbm, 104 mhz input sine wave shown satisfies this requirement. recommended parameters for the various gsm/pcs/dcs synthesizers are given in table 9 . table 9. recommended setup parameters gsm900 dcs1800/pcs1900 parameter tx rx tx rx loop bw 60 khz 40 khz 60 khz 40 khz pfd (mhz) 13 26 13 13 mod 65 130 65 65 dither off off off off prescaler 4/5 4/5 8/9 8/9 icp timer 28 78 28 38 sw1, sw2, sw3 timers 35 85 35 45 vco k v 18 mhz/v 18 mhz/v 38 mhz/v 38 mhz/v loop bw and pfd frequency a 60 khz loop bw is narrow enough to attenuate the pll phase noise and spurs to the required level for a tx low. a 40 khz bw is necessary to meet the gsm900 rx synthesizers particularly tough phase noise and spur requirements at 800 khz offsets. to get the lowest spur levels at 800 khz offsets for rx, the - modulator should be run at the highest oversampling rate possible. therefore, for gsm900 rx, a 26 mhz pfd frequency is chosen and mod = 130 is required for 200 khz steps. because this value of mod is divisible by two, certain frac channels have a 100 khz fractional spur. this is attenuated by the 40 khz loop filter and therefore is not a concern. however, the 60 khz loop filter recommended for tx has a closed-loop response that peaks close to 100 khz. therefore, a 13 mhz pfd with mod = 65, which avoids the 100 khz spur, is the best choice for a tx synthesizer. dither dither off should be selected for the lowest rms phase error. prescaler the 8/9 prescaler should be selected for the pcs and dcs bands. the 4/5 prescaler allows an n divider range low enough to cover the gsm900 tx and rx bands with either a 13 mhz or 26 mhz pfd frequency. timer values for tx to comply with the gsm spectrum due to switching require- ments, the tx synthesizer should not switch frequency until the pa output power has ramped down by at least 50 db. if it takes 10 s to ramp down to this level, then only the last 20 s of the 30 s guard period is available for the tx synthesizer to lock to final frequency and phase. in fast lock mode, the tx loop bw is widened by a factor-of-8 to 480 khz, and therefore, the pll achieves frequency lock for a jump across the entire band in <6 s. after this, the pa power can start to ramp up again, and the loop bw can be restored to the final value. with the icp timer = 28, the charge pump current reduction begins at ~8.6 s. when sw1, sw2, and sw3 timers = 35, the current reaches its final value before the loop filter switches open at ~10.8 s. with these timer values, the phase disturbance created when the bandwidth is reduced settles back to its final value by 20 s, in time for the start of the active part of the gsm burst. if faster phase settling is desired with the 60 khz bw setting, then the timer values can be reduced further but should not be brought less than the 6 s it takes to achieve frequency lock in wide bw mode. timer values for rx the 40 khz rx loop bw is increased by a factor-of-8 to approximately 320 khz during fast lock. with the rx timer values shown, the bw is reduced after ~12 s, which allows sufficient time for the phase disturbance to settle back before the start of the active part of the rx time slot at 30 s. as in the tx case, faster rx settling can be achieved by reducing these timer values, their lower limit being determined by the time it takes to achieve frequency lock in wide bw mode. in addition, the pcs and dcs rx synthesizers have relaxed 800 khz blocker specifications and thus can tolerate a wider loop bw, which allows correspondingly faster settling. vco k v in general, the vco gain, k v , should be set as low as possible to minimize the reference and integer boundary spur levels that arise due to feedthrough mechanisms. when deciding on the optimum vco k v , a good choice is to allow 2 v to tune across the desired band, centered on the available tuning range. with v p 3 regulated to 5.5 v 100 mv, the tuning range available is 2.8 v. loop filter components it is important for good settling performance that capacitors with low dielectric absorption are used in the loop filter. ceramic npo cog capacitors are a good choice for this application. a 2% tolerance is recommended for loop filter capacitors and 1% for resistors. a 10% tolerance is adequate for the inductor, l1.
adf4193 rev. b | page 26 of 28 adi simpll support the adf4193 loop filter design is supported on adi simpll v2.7 or later. example files for popular applications are available for download from the applications section of the adf4193 product page. also available is a technical note ( adf4193-tn-001 ) that outlines a loop filter design procedure that takes full advantage of the new degree of freedom in the filter design that the differential amplifier and loop filter switches provide. 05328-037 r set 23 mux out 16 sw2 27 sw gnd 28 sw1 29 cp out+ 30 cp out? 26 ref in 11 rfin? 5 rfin+ 6 clk 17 sd gnd 14 a gnd 4, 22 d gnd 9, 12, 21 lock detect out data 18 le 19 reference 104mhz, +5dbm adf4193 svd v dd 15 dv dd 8, 10, 13 v p 1 20 v p 2 24 av dd 7 v p 3 32 r set 2.40k ? ain+ ain? 31 25 3 2 a out sw3 integrated differential amplifier c1b 120pf c1a 120pf c3 470pf 100nf 1 cmr ct 30pf r1b1 820 ? r1b2 6.20k ? r1a2 6.20k ? r1a2 820 ? c2b 1.20nf c2a 1.20nf r3 62? r2 1.80k ? l1 2.2mh sirenza vco190-1843t 38mhz/v 100pf 100pf 1nf 1nf 51? 51 ? 100nf 10f + 10f + 100nf 100nf 100nf 100pf 10f + 100nf 100nf 3v 5v 5.5v 10p f 100p f 18 ? 18? 18? rf out figure 36. local oscillator for dcs1800 tx using the adf4193
adf4193 rev. b | page 27 of 28 interfacing the adf4193 has a simple spi?-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 24 bits that have been clocked into the input register on each rising edge of clk are latched into the appropriate register. see figure 2 for the timing diagram and table 5 for the register address table. the maximum allowable serial clock rate is 33 mhz. aduc812 interface figure 37 shows the interface between the adf4193 and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. some registers of the adf4193 require a 24-bit programming word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte is written, the le input should be brought high to complete the transfer. an i/o port line on the aduc812 can also be used to detect lock (mux out configured as lock detect and polled by the port input). aduc812 adf4193 sclock clk data le mux out (lock detect) mosi i/o ports 05328-033 figure 37. aduc812 to adf4193 interface adsp-21xx interface figure 38 shows the interface between the adf4193 and the adsp-21xx digital signal processor. the adf4193 needs a 24-bit serial word for some writes. the easiest way to accom- plish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 24-bit word. to program each 24-bit word, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. adsp-21xx adf4193 sclk clk data le mux out (lock detect) dt tfs i/o flags 05328-034 figure 38. adsp-21xx to adf4193 interface pcb design guidelines for chip scale package the lands on the chip scale package (cp-32-3) are rectangular. the printed circuit board (pcb) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. the land should be centered on the pad. this ensures that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as the exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, they should be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter should be be tween 0.3 mm and 0.33 mm, and the via barrel should be plated with one ounce copper to plug the via. the user should connect the pcb thermal pad to a gnd .
adf4193 rev. b | page 28 of 28 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.45 3.30 sq 3.15 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 39. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-3) dimensions shown in millimeters ordering guide model temperature range package description package option ADF4193BCPZ 1 C40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ADF4193BCPZ-rl 1 C40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 ADF4193BCPZ-rl7 1 C40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-3 eval-adf4193eb1 evaluation board (gsm 1800) eval-adf4193eb2 evaluation board (no vco or loop filter) t 1 z = pb-free part. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05328-0-6/06(b) ttt

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